VHDL Design Engineer West Lothian, Jobs, 4261

VHDL Design Engineer - West Lothian - Central Belt

VHDL Design Engineer - West Lothian - Central Belt

£32,000 - £55,000

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Date Job Posted Tuesday 31 Mar 2020
Reference 4261
Category Telcoms/VOIP
Salary £32,000 - £55,000
Employment Type Permanent

Be-IT's client is a highly successful and forward thinking company working with an enviable client portfolio and has an excellent reputation for producing world class software solutions. Working from their state-of-the-art R&D facility you will join a team of technical experts that prides itself on delivering top quality technical results for clients.

Engineers work in multi-discipline product development teams that include software and hardware design and system test Engineers. The teams work closely with marketing and sales, turning market and customer requirements into high quality, winning products.

We have an exciting opportunity for a VHDL Design Engineer to join the R&D team. In this role you will develop highly performant VHDL targeting the latest FGPA architectures. You will work as part of our multi-discipline product design teams to deliver new products and enhancements to our existing portfolio. The successful candidate will be experienced and able to innovate and deliver in a fast paced and busy environment and enjoy working on leading edge digital designs.


  • Creating new high speed FPGA based digital designs and/or modifying existing designs to support delivery of new product features as per specification.
  • Estimating timescales based on an outline of the requirements and then delivering to those timescales.
  • Support quality oriented activities to deliver a product that will delight our customers.

Skills and Experience

  • Educated to Degree level in Electronics or equivalent subject.
  • Proven VHDL experience on high speed designs with complex clocking architectures.
  • Ability to define digital architectures from a product specification.
  • Ability to work closely with others in a multi-discipline team.
  • Detail orientated and driven to deliver in dynamic environment.


  • Large, complex designs on Xilinx Ultrascale and/or Ultrascale+ series using Vivado & ModelSim.
  • Matching execution times and path delays.
  • Board level schematic design incorporating Microprocessor, DDR, QDR SRAM/SDRAM.
  • Knowledge of Ethernet packet

Please call Alastair Philp directly on 0131 344 4792 for immediate consideration or email your CV to alastair.philp@be-it.co.uk

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